{"datasheet":{"id":"ds_0f73eabcae531d8c17f1","componentName":"MPU-6000","manufacturer":"InvenSense","mpn":"MPU-6000","productFamily":"MPU-60X0","description":"Integrated 6-axis motion processor combining a 3-axis gyroscope and a 3-axis accelerometer with an onboard Digital Motion Processor (DMP).","category":"Sensors","interfaces":["I2C","SPI"],"packageOrModule":"QFN","aliases":["MPU-6050","MPU-60X0"],"chunkCount":161,"imageCount":60,"originalFilename":"MPU-6050 Datasheet.PDF","createdAt":"2026-05-25T15:49:11.194Z","publishedAt":"2026-05-25T15:49:11.194Z","shareUrl":"https://www.embedr.app/datasheets/ds_0f73eabcae531d8c17f1","pagePath":"/datasheets/ds_0f73eabcae531d8c17f1","images":[{"path":"images/260f74d9a6084473248ab9e1f1fb8c7bb34eafb966cbc23419fb3104a2e5308f.jpg","name":"260f74d9a6084473248ab9e1f1fb8c7bb34eafb966cbc23419fb3104a2e5308f.jpg","mimeType":"image/jpeg","semanticKind":"text_snippet","semanticCaption":"Mathematical formula for factory trim calculation","viewUrl":"https://www.embedr.app/api/datasheets/ds_0f73eabcae531d8c17f1/asset?path=images%2F260f74d9a6084473248ab9e1f1fb8c7bb34eafb966cbc23419fb3104a2e5308f.jpg"},{"path":"images/4cd33fafe04edad876372402f142ab9c35ec89245ca45a11e632e066a20b704a.jpg","name":"4cd33fafe04edad876372402f142ab9c35ec89245ca45a11e632e066a20b704a.jpg","mimeType":"image/jpeg","semanticKind":"text_snippet","semanticCaption":"Self-test response percentage change formula","viewUrl":"https://www.embedr.app/api/datasheets/ds_0f73eabcae531d8c17f1/asset?path=images%2F4cd33fafe04edad876372402f142ab9c35ec89245ca45a11e632e066a20b704a.jpg"},{"path":"images/e65de38a00792243534700724ea510603bc9800cc53b33332af1b3918bdc7d94.jpg","name":"e65de38a00792243534700724ea510603bc9800cc53b33332af1b3918bdc7d94.jpg","mimeType":"image/jpeg","semanticKind":"text_snippet","semanticCaption":"Text snippet containing the word 'where,'","viewUrl":"https://www.embedr.app/api/datasheets/ds_0f73eabcae531d8c17f1/asset?path=images%2Fe65de38a00792243534700724ea510603bc9800cc53b33332af1b3918bdc7d94.jpg"},{"path":"images/7e64a71d28c1771e7f74a411121aea8f89342c52b42365c24fbd0a6a1d565a14.jpg","name":"7e64a71d28c1771e7f74a411121aea8f89342c52b42365c24fbd0a6a1d565a14.jpg","mimeType":"image/jpeg","semanticKind":"electrical_table","semanticCaption":"I2C Master Clock Speed and Divider table","viewUrl":"https://www.embedr.app/api/datasheets/ds_0f73eabcae531d8c17f1/asset?path=images%2F7e64a71d28c1771e7f74a411121aea8f89342c52b42365c24fbd0a6a1d565a14.jpg"},{"path":"images/9d0c446276658bc1e40d1aae69db85810f25e3d722975a961434d5f9db466c62.jpg","name":"9d0c446276658bc1e40d1aae69db85810f25e3d722975a961434d5f9db466c62.jpg","mimeType":"image/jpeg","semanticKind":"logo","semanticCaption":"InvenSense document header with logo and document info","viewUrl":"https://www.embedr.app/api/datasheets/ds_0f73eabcae531d8c17f1/asset?path=images%2F9d0c446276658bc1e40d1aae69db85810f25e3d722975a961434d5f9db466c62.jpg"},{"path":"images/71af85c9ad71455074ca016c2a40c45d342fb034e4f169dff628560c24df9ac3.jpg","name":"71af85c9ad71455074ca016c2a40c45d342fb034e4f169dff628560c24df9ac3.jpg","mimeType":"image/jpeg","semanticKind":"register_table","semanticCaption":"Register bit-field map for address 0x68","viewUrl":"https://www.embedr.app/api/datasheets/ds_0f73eabcae531d8c17f1/asset?path=images%2F71af85c9ad71455074ca016c2a40c45d342fb034e4f169dff628560c24df9ac3.jpg"},{"path":"images/2f77f08d473ec906febb0dd76cb042272dbe70aace069c00fd1839bf8f7ff0b7.jpg","name":"2f77f08d473ec906febb0dd76cb042272dbe70aace069c00fd1839bf8f7ff0b7.jpg","mimeType":"image/jpeg","semanticKind":"register_table","semanticCaption":"Register 1C (28) bit field map","viewUrl":"https://www.embedr.app/api/datasheets/ds_0f73eabcae531d8c17f1/asset?path=images%2F2f77f08d473ec906febb0dd76cb042272dbe70aace069c00fd1839bf8f7ff0b7.jpg"},{"path":"images/9ef3f2fc7f77ae4802a5a00372d9e0634efd1bd5260a5da6d44a69cb535dd394.jpg","name":"9ef3f2fc7f77ae4802a5a00372d9e0634efd1bd5260a5da6d44a69cb535dd394.jpg","mimeType":"image/jpeg","semanticKind":"text_snippet","semanticCaption":"FIFO enable bit descriptions","viewUrl":"https://www.embedr.app/api/datasheets/ds_0f73eabcae531d8c17f1/asset?path=images%2F9ef3f2fc7f77ae4802a5a00372d9e0634efd1bd5260a5da6d44a69cb535dd394.jpg"},{"path":"images/adccffc11238fc7e268f18771e96b653b67f2f98a96c03f2b52e123f9f50bec9.jpg","name":"adccffc11238fc7e268f18771e96b653b67f2f98a96c03f2b52e123f9f50bec9.jpg","mimeType":"image/jpeg","semanticKind":"register_table","semanticCaption":"Register 6B (107) bit field map","viewUrl":"https://www.embedr.app/api/datasheets/ds_0f73eabcae531d8c17f1/asset?path=images%2Fadccffc11238fc7e268f18771e96b653b67f2f98a96c03f2b52e123f9f50bec9.jpg"},{"path":"images/e0561aa7bf230752c0db5f8102f369b3d37b4d79fdcf3b59f3db215e0ad484c9.jpg","name":"e0561aa7bf230752c0db5f8102f369b3d37b4d79fdcf3b59f3db215e0ad484c9.jpg","mimeType":"image/jpeg","semanticKind":"register_table","semanticCaption":"Register 75 (117) WHO_AM_I bit field map","viewUrl":"https://www.embedr.app/api/datasheets/ds_0f73eabcae531d8c17f1/asset?path=images%2Fe0561aa7bf230752c0db5f8102f369b3d37b4d79fdcf3b59f3db215e0ad484c9.jpg"},{"path":"images/11e7c62749ff4c76d21142be1857b06bc6662c2bed96eb33c30f2313d0027713.jpg","name":"11e7c62749ff4c76d21142be1857b06bc6662c2bed96eb33c30f2313d0027713.jpg","mimeType":"image/jpeg","semanticKind":"text_snippet","semanticCaption":"I2C slave delay enable bit descriptions","viewUrl":"https://www.embedr.app/api/datasheets/ds_0f73eabcae531d8c17f1/asset?path=images%2F11e7c62749ff4c76d21142be1857b06bc6662c2bed96eb33c30f2313d0027713.jpg"},{"path":"images/d4d90547f0d6d8fe20fe23b7509a84f4787ce7b175a5e6471880813617e23a80.jpg","name":"d4d90547f0d6d8fe20fe23b7509a84f4787ce7b175a5e6471880813617e23a80.jpg","mimeType":"image/jpeg","semanticKind":"register_table","semanticCaption":"Register 64 (100) I2C_SLV1_DO bit field map","viewUrl":"https://www.embedr.app/api/datasheets/ds_0f73eabcae531d8c17f1/asset?path=images%2Fd4d90547f0d6d8fe20fe23b7509a84f4787ce7b175a5e6471880813617e23a80.jpg"},{"path":"images/774513a7e1680853e9f20763c2e4b5276b2cf10d6454f1be644e45e3ec94d814.jpg","name":"774513a7e1680853e9f20763c2e4b5276b2cf10d6454f1be644e45e3ec94d814.jpg","mimeType":"image/jpeg","semanticKind":"register_table","semanticCaption":"Bit-field definition for register 36 (Hex) / 54 (Decimal)","viewUrl":"https://www.embedr.app/api/datasheets/ds_0f73eabcae531d8c17f1/asset?path=images%2F774513a7e1680853e9f20763c2e4b5276b2cf10d6454f1be644e45e3ec94d814.jpg"},{"path":"images/99cb2f408edeaba429ad6d47434baac44a81306d737dab31587c3385d47faa1d.jpg","name":"99cb2f408edeaba429ad6d47434baac44a81306d737dab31587c3385d47faa1d.jpg","mimeType":"image/jpeg","semanticKind":"text_snippet","semanticCaption":"Document header for MPU-6000/MPU-6050 Register Map","viewUrl":"https://www.embedr.app/api/datasheets/ds_0f73eabcae531d8c17f1/asset?path=images%2F99cb2f408edeaba429ad6d47434baac44a81306d737dab31587c3385d47faa1d.jpg"},{"path":"images/6f9d1d36dc0efdcb4a63f986d94ddfa413098eb87687bd84690805e9fef179ce.jpg","name":"6f9d1d36dc0efdcb4a63f986d94ddfa413098eb87687bd84690805e9fef179ce.jpg","mimeType":"image/jpeg","semanticKind":"text_snippet","semanticCaption":"Detailed bit descriptions for interrupt configuration registers","viewUrl":"https://www.embedr.app/api/datasheets/ds_0f73eabcae531d8c17f1/asset?path=images%2F6f9d1d36dc0efdcb4a63f986d94ddfa413098eb87687bd84690805e9fef179ce.jpg"},{"path":"images/4febb440b43e6ad9d62ddfbe1191767f291e5315c921bea54903d83d1b082ab3.jpg","name":"4febb440b43e6ad9d62ddfbe1191767f291e5315c921bea54903d83d1b082ab3.jpg","mimeType":"image/jpeg","semanticKind":"text_snippet","semanticCaption":"Document revision history table","viewUrl":"https://www.embedr.app/api/datasheets/ds_0f73eabcae531d8c17f1/asset?path=images%2F4febb440b43e6ad9d62ddfbe1191767f291e5315c921bea54903d83d1b082ab3.jpg"},{"path":"images/c5a95d31d960e57810fc9951b152851e6fbe966c21ffe31bfa2e097d9d7f72b3.jpg","name":"c5a95d31d960e57810fc9951b152851e6fbe966c21ffe31bfa2e097d9d7f72b3.jpg","mimeType":"image/jpeg","semanticKind":"register_table","semanticCaption":"Bit-field definition for register 6C (Hex) / 108 (Decimal)","viewUrl":"https://www.embedr.app/api/datasheets/ds_0f73eabcae531d8c17f1/asset?path=images%2Fc5a95d31d960e57810fc9951b152851e6fbe966c21ffe31bfa2e097d9d7f72b3.jpg"},{"path":"images/afe60f0137a85387bd61acb1301d9eca4e348d2f252ecb981de784dbf1841187.jpg","name":"afe60f0137a85387bd61acb1301d9eca4e348d2f252ecb981de784dbf1841187.jpg","mimeType":"image/jpeg","semanticKind":"register_table","semanticCaption":"Bit-field definition for register 67 (Hex) / 103 (Decimal)","viewUrl":"https://www.embedr.app/api/datasheets/ds_0f73eabcae531d8c17f1/asset?path=images%2Fafe60f0137a85387bd61acb1301d9eca4e348d2f252ecb981de784dbf1841187.jpg"},{"path":"images/8c5793f080120d3b5706163b33f2e57f5c4c9d5f9d3e8767dd1c643635756f8f.jpg","name":"8c5793f080120d3b5706163b33f2e57f5c4c9d5f9d3e8767dd1c643635756f8f.jpg","mimeType":"image/jpeg","semanticKind":"text_snippet","semanticCaption":"Register bit descriptions for power management and clock selection","viewUrl":"https://www.embedr.app/api/datasheets/ds_0f73eabcae531d8c17f1/asset?path=images%2F8c5793f080120d3b5706163b33f2e57f5c4c9d5f9d3e8767dd1c643635756f8f.jpg"},{"path":"images/68e02dd093011e0f80ce921504bf5d4065b599b1a9e650bcff24a7bc2ea89309.jpg","name":"68e02dd093011e0f80ce921504bf5d4065b599b1a9e650bcff24a7bc2ea89309.jpg","mimeType":"image/jpeg","semanticKind":"text_snippet","semanticCaption":"Definition of FT (Factory Trim) value","viewUrl":"https://www.embedr.app/api/datasheets/ds_0f73eabcae531d8c17f1/asset?path=images%2F68e02dd093011e0f80ce921504bf5d4065b599b1a9e650bcff24a7bc2ea89309.jpg"},{"path":"images/4edee1246187c08dd89b62a708da16e9b363e1fba120e7796e0b6cbfe58b957e.jpg","name":"4edee1246187c08dd89b62a708da16e9b363e1fba120e7796e0b6cbfe58b957e.jpg","mimeType":"image/jpeg","semanticKind":"register_table","semanticCaption":"Register map for FIFO_DATA register","viewUrl":"https://www.embedr.app/api/datasheets/ds_0f73eabcae531d8c17f1/asset?path=images%2F4edee1246187c08dd89b62a708da16e9b363e1fba120e7796e0b6cbfe58b957e.jpg"},{"path":"images/54b1bf5fcd25106aee536a71c9dd9358f2de593fe8236ff485b6d2a98161671c.jpg","name":"54b1bf5fcd25106aee536a71c9dd9358f2de593fe8236ff485b6d2a98161671c.jpg","mimeType":"image/jpeg","semanticKind":"register_table","semanticCaption":"Register map for TEMP_OUT high and low bytes","viewUrl":"https://www.embedr.app/api/datasheets/ds_0f73eabcae531d8c17f1/asset?path=images%2F54b1bf5fcd25106aee536a71c9dd9358f2de593fe8236ff485b6d2a98161671c.jpg"},{"path":"images/27bec47ed930e29c5b94342c42cab82dc68b5d175a9ed79aed38140ba5a0bb20.jpg","name":"27bec47ed930e29c5b94342c42cab82dc68b5d175a9ed79aed38140ba5a0bb20.jpg","mimeType":"image/jpeg","semanticKind":"text_snippet","semanticCaption":"Descriptions for slave FIFO enable bits","viewUrl":"https://www.embedr.app/api/datasheets/ds_0f73eabcae531d8c17f1/asset?path=images%2F27bec47ed930e29c5b94342c42cab82dc68b5d175a9ed79aed38140ba5a0bb20.jpg"},{"path":"images/a08bfceba78e79067fe24fa31a15b18c1340d454741ddf26bb883a1abeb4a514.jpg","name":"a08bfceba78e79067fe24fa31a15b18c1340d454741ddf26bb883a1abeb4a514.jpg","mimeType":"image/jpeg","semanticKind":"text_snippet","semanticCaption":"I2C Slave 4 control register bit descriptions","viewUrl":"https://www.embedr.app/api/datasheets/ds_0f73eabcae531d8c17f1/asset?path=images%2Fa08bfceba78e79067fe24fa31a15b18c1340d454741ddf26bb883a1abeb4a514.jpg"},{"path":"images/90676fbe3235a8fa94ac85657b529ee4f1e345c56a24ee2964cabd87241a2271.jpg","name":"90676fbe3235a8fa94ac85657b529ee4f1e345c56a24ee2964cabd87241a2271.jpg","mimeType":"image/jpeg","semanticKind":"register_table","semanticCaption":"EXT_SYNC_SET configuration table for FSYNC bit location","viewUrl":"https://www.embedr.app/api/datasheets/ds_0f73eabcae531d8c17f1/asset?path=images%2F90676fbe3235a8fa94ac85657b529ee4f1e345c56a24ee2964cabd87241a2271.jpg"},{"path":"images/8fff46158a8190914f4a76f651d10733eb5de5f5b9125a90febe0344e01d1dd5.jpg","name":"8fff46158a8190914f4a76f651d10733eb5de5f5b9125a90febe0344e01d1dd5.jpg","mimeType":"image/jpeg","semanticKind":"register_table","semanticCaption":"Bit-field definition for SMPLRT_DIV register","viewUrl":"https://www.embedr.app/api/datasheets/ds_0f73eabcae531d8c17f1/asset?path=images%2F8fff46158a8190914f4a76f651d10733eb5de5f5b9125a90febe0344e01d1dd5.jpg"},{"path":"images/0c277ab74a0c4af0c432d8d432dc0f867077d5bff00f30a9bccf3640b919101a.jpg","name":"0c277ab74a0c4af0c432d8d432dc0f867077d5bff00f30a9bccf3640b919101a.jpg","mimeType":"image/jpeg","semanticKind":"text_snippet","semanticCaption":"Descriptions of I2C master and sensor data register bits","viewUrl":"https://www.embedr.app/api/datasheets/ds_0f73eabcae531d8c17f1/asset?path=images%2F0c277ab74a0c4af0c432d8d432dc0f867077d5bff00f30a9bccf3640b919101a.jpg"},{"path":"images/2b7d211156efeec1eb6b904be74bd49e6131b04e7c40db7b8dba7c8e26d39411.jpg","name":"2b7d211156efeec1eb6b904be74bd49e6131b04e7c40db7b8dba7c8e26d39411.jpg","mimeType":"image/jpeg","semanticKind":"text_snippet","semanticCaption":"Formula for SelfTest Response calculation","viewUrl":"https://www.embedr.app/api/datasheets/ds_0f73eabcae531d8c17f1/asset?path=images%2F2b7d211156efeec1eb6b904be74bd49e6131b04e7c40db7b8dba7c8e26d39411.jpg"},{"path":"images/02f66674215543ec34ae4ba2e9b488251010f974b45458d3f692e1fd298e1234.jpg","name":"02f66674215543ec34ae4ba2e9b488251010f974b45458d3f692e1fd298e1234.jpg","mimeType":"image/jpeg","semanticKind":"register_table","semanticCaption":"Comprehensive register map showing addresses and bit-fields","viewUrl":"https://www.embedr.app/api/datasheets/ds_0f73eabcae531d8c17f1/asset?path=images%2F02f66674215543ec34ae4ba2e9b488251010f974b45458d3f692e1fd298e1234.jpg"},{"path":"images/240ed5deea98e26e634b2eb5ddc4e4d9969e1e85292d7c6abdc6f8341e329df9.jpg","name":"240ed5deea98e26e634b2eb5ddc4e4d9969e1e85292d7c6abdc6f8341e329df9.jpg","mimeType":"image/jpeg","semanticKind":"logo","semanticCaption":"InvenSense MPU-6000/MPU-6050 datasheet header","viewUrl":"https://www.embedr.app/api/datasheets/ds_0f73eabcae531d8c17f1/asset?path=images%2F240ed5deea98e26e634b2eb5ddc4e4d9969e1e85292d7c6abdc6f8341e329df9.jpg"},{"path":"images/815431b9fb587ae88694208ce23b6eba8dd1718e45698ee84e3c42c66675128a.jpg","name":"815431b9fb587ae88694208ce23b6eba8dd1718e45698ee84e3c42c66675128a.jpg","mimeType":"image/jpeg","semanticKind":"text_snippet","semanticCaption":"SelfTest Response text snippet","viewUrl":"https://www.embedr.app/api/datasheets/ds_0f73eabcae531d8c17f1/asset?path=images%2F815431b9fb587ae88694208ce23b6eba8dd1718e45698ee84e3c42c66675128a.jpg"},{"path":"images/7c5faa5f4448b7a7e9938b743a7a946d63862948cc83a18cb1fd2cd5a03eedf2.jpg","name":"7c5faa5f4448b7a7e9938b743a7a946d63862948cc83a18cb1fd2cd5a03eedf2.jpg","mimeType":"image/jpeg","semanticKind":"electrical_table","semanticCaption":"Accelerometer full scale range selection table","viewUrl":"https://www.embedr.app/api/datasheets/ds_0f73eabcae531d8c17f1/asset?path=images%2F7c5faa5f4448b7a7e9938b743a7a946d63862948cc83a18cb1fd2cd5a03eedf2.jpg"},{"path":"images/25df7d09840d1b24fe35b29743fb38d2774c84aa4f3a7ee6a7f7aa78c24ef32c.jpg","name":"25df7d09840d1b24fe35b29743fb38d2774c84aa4f3a7ee6a7f7aa78c24ef32c.jpg","mimeType":"image/jpeg","semanticKind":"text_snippet","semanticCaption":"Document header for MPU-6000/MPU-6050 Register Map","viewUrl":"https://www.embedr.app/api/datasheets/ds_0f73eabcae531d8c17f1/asset?path=images%2F25df7d09840d1b24fe35b29743fb38d2774c84aa4f3a7ee6a7f7aa78c24ef32c.jpg"},{"path":"images/57829334d70062e06cd946d891ba8133fcef5ecb5f920d28f693621fc791b149.jpg","name":"57829334d70062e06cd946d891ba8133fcef5ecb5f920d28f693621fc791b149.jpg","mimeType":"image/jpeg","semanticKind":"register_table","semanticCaption":"Bit-field definition for register 0x6A (USER_CTRL)","viewUrl":"https://www.embedr.app/api/datasheets/ds_0f73eabcae531d8c17f1/asset?path=images%2F57829334d70062e06cd946d891ba8133fcef5ecb5f920d28f693621fc791b149.jpg"},{"path":"images/28a8f996adc8bc56f62963f11c5777f82235bd3c1f8c8837b8cfc04d56d8ac2e.jpg","name":"28a8f996adc8bc56f62963f11c5777f82235bd3c1f8c8837b8cfc04d56d8ac2e.jpg","mimeType":"image/jpeg","semanticKind":"text_snippet","semanticCaption":"Document header for MPU-6000/MPU-6050 Register Map","viewUrl":"https://www.embedr.app/api/datasheets/ds_0f73eabcae531d8c17f1/asset?path=images%2F28a8f996adc8bc56f62963f11c5777f82235bd3c1f8c8837b8cfc04d56d8ac2e.jpg"},{"path":"images/d1c95461ba03baeb203b71f13839a1cf12b341117a151cffae3aa1f3e3402e86.jpg","name":"d1c95461ba03baeb203b71f13839a1cf12b341117a151cffae3aa1f3e3402e86.jpg","mimeType":"image/jpeg","semanticKind":"register_table","semanticCaption":"Bit-field definition for register 0x66 (I2C_SLV3_DO)","viewUrl":"https://www.embedr.app/api/datasheets/ds_0f73eabcae531d8c17f1/asset?path=images%2Fd1c95461ba03baeb203b71f13839a1cf12b341117a151cffae3aa1f3e3402e86.jpg"},{"path":"images/cb7df8741ee297461138effbb74cd8592769d0bcf44c8641db8a4de476e67c6a.jpg","name":"cb7df8741ee297461138effbb74cd8592769d0bcf44c8641db8a4de476e67c6a.jpg","mimeType":"image/jpeg","semanticKind":"register_table","semanticCaption":"Register map table showing addresses 0x67 to 0x75","viewUrl":"https://www.embedr.app/api/datasheets/ds_0f73eabcae531d8c17f1/asset?path=images%2Fcb7df8741ee297461138effbb74cd8592769d0bcf44c8641db8a4de476e67c6a.jpg"},{"path":"images/495de374043ab12465bd64f4a8fc52bea90f04d4aef1c94df53f03ea0b33b5d0.jpg","name":"495de374043ab12465bd64f4a8fc52bea90f04d4aef1c94df53f03ea0b33b5d0.jpg","mimeType":"image/jpeg","semanticKind":"register_table","semanticCaption":"Register bit definitions for I2C Slave 3 configuration","viewUrl":"https://www.embedr.app/api/datasheets/ds_0f73eabcae531d8c17f1/asset?path=images%2F495de374043ab12465bd64f4a8fc52bea90f04d4aef1c94df53f03ea0b33b5d0.jpg"},{"path":"images/981d930454feb5872ca75eda4ff95e6865c20055bdb908e0b71f95e0cc4382d6.jpg","name":"981d930454feb5872ca75eda4ff95e6865c20055bdb908e0b71f95e0cc4382d6.jpg","mimeType":"image/jpeg","semanticKind":"register_table","semanticCaption":"Register map for sensor data and external sensor data registers","viewUrl":"https://www.embedr.app/api/datasheets/ds_0f73eabcae531d8c17f1/asset?path=images%2F981d930454feb5872ca75eda4ff95e6865c20055bdb908e0b71f95e0cc4382d6.jpg"},{"path":"images/71e1f6b7cdab431c9d15e8be0f4a9e11962d62c483bddfbfafdf35285c4c7add.jpg","name":"71e1f6b7cdab431c9d15e8be0f4a9e11962d62c483bddfbfafdf35285c4c7add.jpg","mimeType":"image/jpeg","semanticKind":"text_snippet","semanticCaption":"Mathematical formula snippet for I2C master delay samples","viewUrl":"https://www.embedr.app/api/datasheets/ds_0f73eabcae531d8c17f1/asset?path=images%2F71e1f6b7cdab431c9d15e8be0f4a9e11962d62c483bddfbfafdf35285c4c7add.jpg"},{"path":"images/58607a8f848570254f13c6f4de09823cd3dee6de484e7ae2dbe4ef3008a21c93.jpg","name":"58607a8f848570254f13c6f4de09823cd3dee6de484e7ae2dbe4ef3008a21c93.jpg","mimeType":"image/jpeg","semanticKind":"register_table","semanticCaption":"FIFO enable register bit definitions","viewUrl":"https://www.embedr.app/api/datasheets/ds_0f73eabcae531d8c17f1/asset?path=images%2F58607a8f848570254f13c6f4de09823cd3dee6de484e7ae2dbe4ef3008a21c93.jpg"},{"path":"images/98a5a64a519f9e35034e350258c6ebd9a097eec51e28237554ce0a1ae7e985c6.jpg","name":"98a5a64a519f9e35034e350258c6ebd9a097eec51e28237554ce0a1ae7e985c6.jpg","mimeType":"image/jpeg","semanticKind":"register_table","semanticCaption":"Interrupt status register bit definitions","viewUrl":"https://www.embedr.app/api/datasheets/ds_0f73eabcae531d8c17f1/asset?path=images%2F98a5a64a519f9e35034e350258c6ebd9a097eec51e28237554ce0a1ae7e985c6.jpg"},{"path":"images/3fe4d10e8fb0089ded0d9c8c5e486c69edeee522e09e194eba3b5b442a9864ce.jpg","name":"3fe4d10e8fb0089ded0d9c8c5e486c69edeee522e09e194eba3b5b442a9864ce.jpg","mimeType":"image/jpeg","semanticKind":"electrical_table","semanticCaption":"Accelerometer full scale range and sensitivity table","viewUrl":"https://www.embedr.app/api/datasheets/ds_0f73eabcae531d8c17f1/asset?path=images%2F3fe4d10e8fb0089ded0d9c8c5e486c69edeee522e09e194eba3b5b442a9864ce.jpg"},{"path":"images/b6ceef93e5381044035565c31aec5e85dff9fc8d3a131eaf4a7aaef89c4de01f.jpg","name":"b6ceef93e5381044035565c31aec5e85dff9fc8d3a131eaf4a7aaef89c4de01f.jpg","mimeType":"image/jpeg","semanticKind":"electrical_table","semanticCaption":"Digital Low Pass Filter (DLPF) configuration table for accelerometer and gyroscope","viewUrl":"https://www.embedr.app/api/datasheets/ds_0f73eabcae531d8c17f1/asset?path=images%2Fb6ceef93e5381044035565c31aec5e85dff9fc8d3a131eaf4a7aaef89c4de01f.jpg"},{"path":"images/4698703f00eaacad5f91a2d2eb17c1b57b32e845a7a406e92b8eb169f3e8231b.jpg","name":"4698703f00eaacad5f91a2d2eb17c1b57b32e845a7a406e92b8eb169f3e8231b.jpg","mimeType":"image/jpeg","semanticKind":"text_snippet","semanticCaption":"Self-test register field descriptions","viewUrl":"https://www.embedr.app/api/datasheets/ds_0f73eabcae531d8c17f1/asset?path=images%2F4698703f00eaacad5f91a2d2eb17c1b57b32e845a7a406e92b8eb169f3e8231b.jpg"},{"path":"images/05a3c46604c71c0dfeaa7bd01a19e3ab492855e9c6310de21a48bcb10c1ee1bc.jpg","name":"05a3c46604c71c0dfeaa7bd01a19e3ab492855e9c6310de21a48bcb10c1ee1bc.jpg","mimeType":"image/jpeg","semanticKind":"register_table","semanticCaption":"I2C Slave 0 control register bit map","viewUrl":"https://www.embedr.app/api/datasheets/ds_0f73eabcae531d8c17f1/asset?path=images%2F05a3c46604c71c0dfeaa7bd01a19e3ab492855e9c6310de21a48bcb10c1ee1bc.jpg"},{"path":"images/43d2c382d5411e043b1dce01977ad88d4f1a15274b78ca83c88355b934aa60c6.jpg","name":"43d2c382d5411e043b1dce01977ad88d4f1a15274b78ca83c88355b934aa60c6.jpg","mimeType":"image/jpeg","semanticKind":"logo","semanticCaption":"InvenSense MPU-6000/MPU-6050 document header","viewUrl":"https://www.embedr.app/api/datasheets/ds_0f73eabcae531d8c17f1/asset?path=images%2F43d2c382d5411e043b1dce01977ad88d4f1a15274b78ca83c88355b934aa60c6.jpg"},{"path":"images/8858def99e402ba522e22ec473b55233107b9fadf4143f141234d9e119664aec.jpg","name":"8858def99e402ba522e22ec473b55233107b9fadf4143f141234d9e119664aec.jpg","mimeType":"image/jpeg","semanticKind":"electrical_table","semanticCaption":"Low power wake-up frequency configuration table","viewUrl":"https://www.embedr.app/api/datasheets/ds_0f73eabcae531d8c17f1/asset?path=images%2F8858def99e402ba522e22ec473b55233107b9fadf4143f141234d9e119664aec.jpg"},{"path":"images/56f9fab5de87d72d679b9a472768fe68eaea9e5dbe2f043d653632bdb39d0a4a.jpg","name":"56f9fab5de87d72d679b9a472768fe68eaea9e5dbe2f043d653632bdb39d0a4a.jpg","mimeType":"image/jpeg","semanticKind":"text_snippet","semanticCaption":"Register bit field descriptions for FIFO and I2C control","viewUrl":"https://www.embedr.app/api/datasheets/ds_0f73eabcae531d8c17f1/asset?path=images%2F56f9fab5de87d72d679b9a472768fe68eaea9e5dbe2f043d653632bdb39d0a4a.jpg"},{"path":"images/1bb8d2634ff849aef9e451e2683a97a2a43d9c526824e6dfec86ce5744f36a86.jpg","name":"1bb8d2634ff849aef9e451e2683a97a2a43d9c526824e6dfec86ce5744f36a86.jpg","mimeType":"image/jpeg","semanticKind":"text_snippet","semanticCaption":"Document header for MPU-6000/MPU-6050 Register Map","viewUrl":"https://www.embedr.app/api/datasheets/ds_0f73eabcae531d8c17f1/asset?path=images%2F1bb8d2634ff849aef9e451e2683a97a2a43d9c526824e6dfec86ce5744f36a86.jpg"},{"path":"images/5a3efc61b38b9c2bc93d7b8cf299e6252faa018b4472094e4d8f2c076b6a90bf.jpg","name":"5a3efc61b38b9c2bc93d7b8cf299e6252faa018b4472094e4d8f2c076b6a90bf.jpg","mimeType":"image/jpeg","semanticKind":"register_table","semanticCaption":"Clock source selection table","viewUrl":"https://www.embedr.app/api/datasheets/ds_0f73eabcae531d8c17f1/asset?path=images%2F5a3efc61b38b9c2bc93d7b8cf299e6252faa018b4472094e4d8f2c076b6a90bf.jpg"},{"path":"images/71c2050cd6f688ee82ffa6acd69072474825121c9f72bb1ac8a54e52b1fcb38c.jpg","name":"71c2050cd6f688ee82ffa6acd69072474825121c9f72bb1ac8a54e52b1fcb38c.jpg","mimeType":"image/jpeg","semanticKind":"register_table","semanticCaption":"Register bit-field map for I2C Slave 2 configuration","viewUrl":"https://www.embedr.app/api/datasheets/ds_0f73eabcae531d8c17f1/asset?path=images%2F71c2050cd6f688ee82ffa6acd69072474825121c9f72bb1ac8a54e52b1fcb38c.jpg"},{"path":"images/f9beed730777d45cbdc103bdebb4d7ab506e9fb7ba6da0f22e97f2156f5299c7.jpg","name":"f9beed730777d45cbdc103bdebb4d7ab506e9fb7ba6da0f22e97f2156f5299c7.jpg","mimeType":"image/jpeg","semanticKind":"text_snippet","semanticCaption":"Detailed bit descriptions for I2C Slave 0 registers","viewUrl":"https://www.embedr.app/api/datasheets/ds_0f73eabcae531d8c17f1/asset?path=images%2Ff9beed730777d45cbdc103bdebb4d7ab506e9fb7ba6da0f22e97f2156f5299c7.jpg"},{"path":"images/970fcb306c69a09a8252b90aaf31fd356ec7776e4d693b772bac0264be470d80.jpg","name":"970fcb306c69a09a8252b90aaf31fd356ec7776e4d693b772bac0264be470d80.jpg","mimeType":"image/jpeg","semanticKind":"electrical_table","semanticCaption":"Gyroscope full scale range and sensitivity table","viewUrl":"https://www.embedr.app/api/datasheets/ds_0f73eabcae531d8c17f1/asset?path=images%2F970fcb306c69a09a8252b90aaf31fd356ec7776e4d693b772bac0264be470d80.jpg"},{"path":"images/0f5be95f8eb4a938010f98ab7d2d269281b8282d5caebeafabefb2b3f57994a6.jpg","name":"0f5be95f8eb4a938010f98ab7d2d269281b8282d5caebeafabefb2b3f57994a6.jpg","mimeType":"image/jpeg","semanticKind":"text_snippet","semanticCaption":"Formula for calculating the change from factory trim of the self-test response","viewUrl":"https://www.embedr.app/api/datasheets/ds_0f73eabcae531d8c17f1/asset?path=images%2F0f5be95f8eb4a938010f98ab7d2d269281b8282d5caebeafabefb2b3f57994a6.jpg"},{"path":"images/25f80b80d4018c1b5374f20c55e89fe664b38705e23cc9840b181ee9b31ad7c6.jpg","name":"25f80b80d4018c1b5374f20c55e89fe664b38705e23cc9840b181ee9b31ad7c6.jpg","mimeType":"image/jpeg","semanticKind":"text_snippet","semanticCaption":"Document header for MPU-6000/MPU-6050 Register Map and Descriptions","viewUrl":"https://www.embedr.app/api/datasheets/ds_0f73eabcae531d8c17f1/asset?path=images%2F25f80b80d4018c1b5374f20c55e89fe664b38705e23cc9840b181ee9b31ad7c6.jpg"},{"path":"images/682ad01dfdfbc17ad99e244eb026ed8f0d686af2229fb6c6720d0fbdc198e612.jpg","name":"682ad01dfdfbc17ad99e244eb026ed8f0d686af2229fb6c6720d0fbdc198e612.jpg","mimeType":"image/jpeg","semanticKind":"register_table","semanticCaption":"Gyroscope output register bit map","viewUrl":"https://www.embedr.app/api/datasheets/ds_0f73eabcae531d8c17f1/asset?path=images%2F682ad01dfdfbc17ad99e244eb026ed8f0d686af2229fb6c6720d0fbdc198e612.jpg"},{"path":"images/84c864576221a2f5a45fbe0c0a1bce31151466ece102c8855818cbc20187f98b.jpg","name":"84c864576221a2f5a45fbe0c0a1bce31151466ece102c8855818cbc20187f98b.jpg","mimeType":"image/jpeg","semanticKind":"text_snippet","semanticCaption":"Descriptions of I2C and interrupt status bits","viewUrl":"https://www.embedr.app/api/datasheets/ds_0f73eabcae531d8c17f1/asset?path=images%2F84c864576221a2f5a45fbe0c0a1bce31151466ece102c8855818cbc20187f98b.jpg"},{"path":"images/5709927601842089bf09192d5d218ff84536c268df372937dcdaa7660f6b0305.jpg","name":"5709927601842089bf09192d5d218ff84536c268df372937dcdaa7660f6b0305.jpg","mimeType":"image/jpeg","semanticKind":"text_snippet","semanticCaption":"Document header for MPU-6000/MPU-6050 Register Map and Descriptions","viewUrl":"https://www.embedr.app/api/datasheets/ds_0f73eabcae531d8c17f1/asset?path=images%2F5709927601842089bf09192d5d218ff84536c268df372937dcdaa7660f6b0305.jpg"},{"path":"images/3b910bcecdafe885e31e4cf19d8dbfcdbfe748b76a50418525793ea5c4c8b5a0.jpg","name":"3b910bcecdafe885e31e4cf19d8dbfcdbfe748b76a50418525793ea5c4c8b5a0.jpg","mimeType":"image/jpeg","semanticKind":"text_snippet","semanticCaption":"Mathematical formula for factory trim calculation","viewUrl":"https://www.embedr.app/api/datasheets/ds_0f73eabcae531d8c17f1/asset?path=images%2F3b910bcecdafe885e31e4cf19d8dbfcdbfe748b76a50418525793ea5c4c8b5a0.jpg"}],"links":{"page":"https://www.embedr.app/datasheets/ds_0f73eabcae531d8c17f1","metadata":"https://www.embedr.app/api/datasheets/ds_0f73eabcae531d8c17f1/metadata","markdown":"https://www.embedr.app/api/datasheets/ds_0f73eabcae531d8c17f1/markdown","pdf":"https://www.embedr.app/api/datasheets/ds_0f73eabcae531d8c17f1/pdf","chunks":"https://www.embedr.app/api/datasheets/ds_0f73eabcae531d8c17f1/chunks","search":"https://www.embedr.app/api/datasheets/ds_0f73eabcae531d8c17f1/search"}}}