{"datasheetId":"ds_5d5844c3162e775bb9bd","nextCursor":"49","chunks":[{"chunkId":"ds_5d5844c3162e775bb9bd-chunk-0001","chunkIndex":0,"heading":"RP2040 Datasheet","headingPath":["RP2040 Datasheet"],"preview":"RP2040 Datasheet A microcontroller by Raspberry Pi Colophon © 2020 2025 Raspberry Pi Ltd (formerly Raspberry Pi (Trading) Ltd.) This documentation is licensed under a Creative Commons Attribution NoDerivatives 4.0 International (CC BY ND).","images":[],"readUrl":"https://www.embedr.app/api/datasheets/ds_5d5844c3162e775bb9bd/chunks/ds_5d5844c3162e775bb9bd-chunk-0001"},{"chunkId":"ds_5d5844c3162e775bb9bd-chunk-0002","chunkIndex":1,"heading":"Legal disclaimer notice","headingPath":["Legal disclaimer notice"],"preview":"Legal disclaimer notice TECHNICAL AND RELIABILITY DATA FOR RASPBERRY PI PRODUCTS (INCLUDING DATASHEETS) AS MODIFIED FROM TIME TO TIME (\"RESOURCES\") ARE PROVIDED BY RASPBERRY PI LTD (\"RPL\") \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCL","images":[],"readUrl":"https://www.embedr.app/api/datasheets/ds_5d5844c3162e775bb9bd/chunks/ds_5d5844c3162e775bb9bd-chunk-0002"},{"chunkId":"ds_5d5844c3162e775bb9bd-chunk-0003","chunkIndex":2,"heading":"Legal disclaimer notice","headingPath":["Legal disclaimer notice"],"preview":"The RESOURCES are intended for skilled users with suitable levels of design knowledge. Users are solely responsible for their selection and use of the RESOURCES and any application of the products described in them. User agrees to indemnify","images":[],"readUrl":"https://www.embedr.app/api/datasheets/ds_5d5844c3162e775bb9bd/chunks/ds_5d5844c3162e775bb9bd-chunk-0003"},{"chunkId":"ds_5d5844c3162e775bb9bd-chunk-0004","chunkIndex":3,"heading":"Legal disclaimer notice","headingPath":["Legal disclaimer notice"],"preview":"HIGH RISK ACTIVITIES. Raspberry Pi products are not designed, manufactured or intended for use in hazardous environments requiring fail safe performance, such as in the operation of nuclear facilities, aircraft navigation or communication s","images":[],"readUrl":"https://www.embedr.app/api/datasheets/ds_5d5844c3162e775bb9bd/chunks/ds_5d5844c3162e775bb9bd-chunk-0004"},{"chunkId":"ds_5d5844c3162e775bb9bd-chunk-0005","chunkIndex":4,"heading":"Table of contents","headingPath":["Table of contents"],"preview":"Table of contents Colophon . Legal disclaimer notice 1. Introduction. 8 1.1. Why is the chip called RP2040?. 8 1.2. Summary 9 1.3. The Chip . 9 1.4. Pinout Reference. 10 1.4.1. Pin Locations . 10 1.4.2. Pin Descriptions . 11 1.4.3. GPIO Fun","images":[],"readUrl":"https://www.embedr.app/api/datasheets/ds_5d5844c3162e775bb9bd/chunks/ds_5d5844c3162e775bb9bd-chunk-0005"},{"chunkId":"ds_5d5844c3162e775bb9bd-chunk-0006","chunkIndex":5,"heading":"2. System Description 14","headingPath":["2. System Description 14"],"preview":"2.6.2. SRAM . 121 2.6.3. Flash . 122 2.7. Boot Sequence . 128 2.8. Bootrom . . 128 2.8.1. Processor Controlled Boot Sequence . . 129 2.8.2. Launching Code On Processor Core 1 . 131 2.8.3. Bootrom Contents . . 132 2.8.4. USB Mass Storage Int","images":[],"readUrl":"https://www.embedr.app/api/datasheets/ds_5d5844c3162e775bb9bd/chunks/ds_5d5844c3162e775bb9bd-chunk-0006"},{"chunkId":"ds_5d5844c3162e775bb9bd-chunk-0007","chunkIndex":6,"heading":"2. System Description 14","headingPath":["2. System Description 14"],"preview":"2.12.2. Power on Reset . 164 2.12.3. Brown out Detection . . 165 2.12.4. Supply Monitor. . . 167 2.12.5. External Reset . 167 2.12.6. Rescue Debug Port Reset. . 167 2.12.7. Source of Last Reset. . 168 2.12.8. List of Registers. . 168 2.13.","images":[],"readUrl":"https://www.embedr.app/api/datasheets/ds_5d5844c3162e775bb9bd/chunks/ds_5d5844c3162e775bb9bd-chunk-0007"},{"chunkId":"ds_5d5844c3162e775bb9bd-chunk-0008","chunkIndex":7,"heading":"2. System Description 14","headingPath":["2. System Description 14"],"preview":"2.17.3. Modifying the frequency. . 222 2.17.4. ROSC divider . 223 2.17.5. Random Number Generator . 223 2.17.6. ROSC Counter 223 2.17.7. DORMANT mode . . 223 2.17.8. List of Registers. 224 2.18. PLL . 228 2.18.1. Overview . . 228 2.18.2. Ca","images":[],"readUrl":"https://www.embedr.app/api/datasheets/ds_5d5844c3162e775bb9bd/chunks/ds_5d5844c3162e775bb9bd-chunk-0008"},{"chunkId":"ds_5d5844c3162e775bb9bd-chunk-0009","chunkIndex":8,"heading":"2. System Description 14","headingPath":["2. System Description 14"],"preview":"3.3.5. Labels . 320 3.3.6. Instructions. . 321 3.3.7. Pseudoinstructions . 321 3.4. Instruction Set . . 321 3.4.1. Summary. . . 321 3.4.2. JMP . . 322 3.4.3. WAIT . 323 3.4.4. IN . . 324 3.4.5. OUT 325 3.4.6. PUSH . . 326 3.4.7. PULL . 327","images":[],"readUrl":"https://www.embedr.app/api/datasheets/ds_5d5844c3162e775bb9bd/chunks/ds_5d5844c3162e775bb9bd-chunk-0009"},{"chunkId":"ds_5d5844c3162e775bb9bd-chunk-0010","chunkIndex":9,"heading":"2. System Description 14","headingPath":["2. System Description 14"],"preview":"4.2.2. Functional description. . . 418 4.2.3. Operation . 420 4.2.4. UART hardware flow control . 422 4.2.5. UART DMA Interface . . 424 4.2.6. Interrupts . 425 4.2.7. Programmer’s Model. . . 427 4.2.8. List of Registers . . 429 4.3. I2C. .","images":[],"readUrl":"https://www.embedr.app/api/datasheets/ds_5d5844c3162e775bb9bd/chunks/ds_5d5844c3162e775bb9bd-chunk-0010"},{"chunkId":"ds_5d5844c3162e775bb9bd-chunk-0011","chunkIndex":10,"heading":"2. System Description 14","headingPath":["2. System Description 14"],"preview":"4.6. Timer . 534 4.6.1. Overview . . 534 4.6.2. Counter . . 535 4.6.3. Alarms. . 535 4.6.4. Programmer’s Model. . 536 4.6.5. List of Registers . 539 4.7. Watchdog. . 544 4.7.1. Overview . . 544 4.7.2. Tick generation . 544 4.7.3. Watchdog C","images":[],"readUrl":"https://www.embedr.app/api/datasheets/ds_5d5844c3162e775bb9bd/chunks/ds_5d5844c3162e775bb9bd-chunk-0011"},{"chunkId":"ds_5d5844c3162e775bb9bd-chunk-0012","chunkIndex":11,"heading":"4.9. ADC and Temperature Sensor. . 557","headingPath":["4.9. ADC and Temperature Sensor. . 557"],"preview":"4.9. ADC and Temperature Sensor. . 557 4.9.1. ADC controller . 558 4.9.2. SAR ADC . . 559 4.9.3. ADC ENOB . 561 4.9.4. INL and DNL . 562 4.9.5. Temperature Sensor . . 563 4.9.6. List of Registers . . 564 4.10. SSI . 567 4.10.1. Overview . .","images":[],"readUrl":"https://www.embedr.app/api/datasheets/ds_5d5844c3162e775bb9bd/chunks/ds_5d5844c3162e775bb9bd-chunk-0012"},{"chunkId":"ds_5d5844c3162e775bb9bd-chunk-0013","chunkIndex":12,"heading":"5. Electrical and Mechanical. 607","headingPath":["5. Electrical and Mechanical. 607"],"preview":"5. Electrical and Mechanical. 607 5.1. Package . . 607 5.1.1. Thermal characteristics . 608 5.1.2. Recommended PCB Footprint 608 5.1.3. Package markings. 608 5.2. Storage conditions . 609 5.3. Solder profile . . . 609 5.4. Compliance . . 61","images":[],"readUrl":"https://www.embedr.app/api/datasheets/ds_5d5844c3162e775bb9bd/chunks/ds_5d5844c3162e775bb9bd-chunk-0013"},{"chunkId":"ds_5d5844c3162e775bb9bd-chunk-0014","chunkIndex":13,"heading":"Appendix A: Register Field Types. 625","headingPath":["Appendix A: Register Field Types. 625"],"preview":"Appendix A: Register Field Types. 625 Standard types . . 625 RW: . . 625 RO: . 625 WO:. . 625 Clear types . 625 SC. . 625 WC . 625 FIFO types . 626 RWF 626 RF . 626 WF . 626 Appendix B: Errata . . 627 Bootrom. 627 RP2040 E9. 627 RP2040 E14","images":[],"readUrl":"https://www.embedr.app/api/datasheets/ds_5d5844c3162e775bb9bd/chunks/ds_5d5844c3162e775bb9bd-chunk-0014"},{"chunkId":"ds_5d5844c3162e775bb9bd-chunk-0015","chunkIndex":14,"heading":"Chapter 1. Introduction","headingPath":["Chapter 1. Introduction"],"preview":"Chapter 1. Introduction Microcontrollers connect the world of software to the world of hardware. They allow developers to write software which interacts with the physical world in the same deterministic, cycle accurate manner as digital log","images":[],"readUrl":"https://www.embedr.app/api/datasheets/ds_5d5844c3162e775bb9bd/chunks/ds_5d5844c3162e775bb9bd-chunk-0015"},{"chunkId":"ds_5d5844c3162e775bb9bd-chunk-0016","chunkIndex":15,"heading":"Chapter 1. Introduction","headingPath":["Chapter 1. Introduction"],"preview":"RP2040 is a stateless device, with support for cached execute in place from external QSPI memory. This design decision allows you to choose the appropriate density of non volatile storage for your application, and to benefit from the low pr","images":[],"readUrl":"https://www.embedr.app/api/datasheets/ds_5d5844c3162e775bb9bd/chunks/ds_5d5844c3162e775bb9bd-chunk-0016"},{"chunkId":"ds_5d5844c3162e775bb9bd-chunk-0017","chunkIndex":16,"heading":"Chapter 1. Introduction","headingPath":["Chapter 1. Introduction"],"preview":"Whatever your microcontroller application, from machine learning to motor control, from agriculture to audio, RP2040 has the performance, feature set, and support to make your product fly. 1.1. Why is the chip called RP2040? The post fix nu","images":[{"path":"images/part_01_be904a60a16f5af1752827ba2b8790e4300d78f424212e7ed74f06481a15a1ad.jpg","name":"part_01_be904a60a16f5af1752827ba2b8790e4300d78f424212e7ed74f06481a15a1ad.jpg","mimeType":"image/jpeg","semanticKind":"unknown","semanticCaption":"Breakdown of the RP2040 model numbering scheme","viewUrl":"https://www.embedr.app/api/datasheets/ds_5d5844c3162e775bb9bd/asset?path=images%2Fpart_01_be904a60a16f5af1752827ba2b8790e4300d78f424212e7ed74f06481a15a1ad.jpg"}],"readUrl":"https://www.embedr.app/api/datasheets/ds_5d5844c3162e775bb9bd/chunks/ds_5d5844c3162e775bb9bd-chunk-0017"},{"chunkId":"ds_5d5844c3162e775bb9bd-chunk-0018","chunkIndex":17,"heading":"1.2. Summary","headingPath":["1.2. Summary"],"preview":"1.2. Summary RP2040 is a low cost, high performance microcontroller device with flexible digital interfaces. Key features: • Dual Cortex M0+ processor cores, up to 133MHz (or 200MHz at 1.15V, see Section 2.15.3) • 264kB of embedded SRAM in","images":[],"readUrl":"https://www.embedr.app/api/datasheets/ds_5d5844c3162e775bb9bd/chunks/ds_5d5844c3162e775bb9bd-chunk-0018"},{"chunkId":"ds_5d5844c3162e775bb9bd-chunk-0019","chunkIndex":18,"heading":"1.3. The Chip","headingPath":["1.3. The Chip"],"preview":"1.3. The Chip RP2040 has a dual M0+ processor cores, DMA, internal memory and peripheral blocks connected via AHB/APB bus fabric. Figure 2. A system overview of the RP2040 chip","images":[],"readUrl":"https://www.embedr.app/api/datasheets/ds_5d5844c3162e775bb9bd/chunks/ds_5d5844c3162e775bb9bd-chunk-0019"},{"chunkId":"ds_5d5844c3162e775bb9bd-chunk-0020","chunkIndex":19,"heading":"1.3. The Chip","headingPath":["1.3. The Chip"],"preview":"AC AF[\"SRAM\"] AC AG[\"SRAM\"] AC AH[\"SRAM\"] AC AI[\"SRAM\"] AC AJ[\"SRAM\"] AC AK[\"SRAM\"] AC AL[\"SRAM\"] AC AM[\"SRAM\"] AC AN[\"SRAM\"] AC AO[\"SRAM\"] AC AP[\"SRAM\"] AC AQ[\"SRAM\"] AC AR[\"SRAM\"] AC AS[\"SRAM\"] AC AT[\"SRAM\"] AC AU[\"SRAM\"] AC AV[\"SRAM\"] AC","images":[],"readUrl":"https://www.embedr.app/api/datasheets/ds_5d5844c3162e775bb9bd/chunks/ds_5d5844c3162e775bb9bd-chunk-0020"},{"chunkId":"ds_5d5844c3162e775bb9bd-chunk-0021","chunkIndex":20,"heading":"1.3. The Chip","headingPath":["1.3. The Chip"],"preview":"AC BZ[\"SRAM\"] AC CA[\"SRAM\"] AC CB[\"SRAM\"] AC CC[\"SRAM\"] AC CD[\"SRAM\"] AC CE[\"SRAM\"] AC CF[\"SRAM\"] AC CG[\"SRAM\"] AC CH[\"SRAM\"] AC CI[\"SRAM\"] AC CJ[\"SRAM\"] AC CK[\"SRAM\"] end subgraph Control L M N end subgraph Data D end subgraph Data E end s","images":[],"readUrl":"https://www.embedr.app/api/datasheets/ds_5d5844c3162e775bb9bd/chunks/ds_5d5844c3162e775bb9bd-chunk-0021"},{"chunkId":"ds_5d5844c3162e775bb9bd-chunk-0022","chunkIndex":21,"heading":"1.3. The Chip","headingPath":["1.3. The Chip"],"preview":"AG end subgraph Data AH end subgraph Data AI end subgraph Data AJ end subgraph Data AK end subgraph Data AL end subgraph Data AM end subgraph Data AN end subgraph Data AO end subgraph Data AP end subgraph Data AQ end subgraph Data AR end su","images":[],"readUrl":"https://www.embedr.app/api/datasheets/ds_5d5844c3162e775bb9bd/chunks/ds_5d5844c3162e775bb9bd-chunk-0022"},{"chunkId":"ds_5d5844c3162e775bb9bd-chunk-0023","chunkIndex":22,"heading":"1.3. The Chip","headingPath":["1.3. The Chip"],"preview":"Internal SRAM can contain code or data. It is addressed as a single 264 kB region, but physically partitioned into 6 banks to allow simultaneous parallel access from different masters. DMA bus masters are available to offload repetitive dat","images":[],"readUrl":"https://www.embedr.app/api/datasheets/ds_5d5844c3162e775bb9bd/chunks/ds_5d5844c3162e775bb9bd-chunk-0023"},{"chunkId":"ds_5d5844c3162e775bb9bd-chunk-0024","chunkIndex":23,"heading":"1.4. Pinout Reference","headingPath":["1.4. Pinout Reference"],"preview":"1.4. Pinout Reference This section provides a quick reference for pinout and pin functions. Full details, including electrical specifications and package drawings, can be found in Chapter 5. 1.4.1. Pin Locations Figure 3. RP2040 Pinout for","images":[],"readUrl":"https://www.embedr.app/api/datasheets/ds_5d5844c3162e775bb9bd/chunks/ds_5d5844c3162e775bb9bd-chunk-0024"},{"chunkId":"ds_5d5844c3162e775bb9bd-chunk-0025","chunkIndex":24,"heading":"1.4.2. Pin Descriptions","headingPath":["1.4.2. Pin Descriptions"],"preview":"","images":[],"readUrl":"https://www.embedr.app/api/datasheets/ds_5d5844c3162e775bb9bd/chunks/ds_5d5844c3162e775bb9bd-chunk-0025"},{"chunkId":"ds_5d5844c3162e775bb9bd-chunk-0026","chunkIndex":25,"heading":"1.4.2. Pin Descriptions","headingPath":["1.4.2. Pin Descriptions"],"preview":"1.4.3. GPIO Functions Each individual GPIO pin can be connected to an internal peripheral via the GPIO functions defined below. Some internal peripheral connections appear in multiple places to allow some system level flexibility. SIO, PIO0","images":[],"readUrl":"https://www.embedr.app/api/datasheets/ds_5d5844c3162e775bb9bd/chunks/ds_5d5844c3162e775bb9bd-chunk-0026"},{"chunkId":"ds_5d5844c3162e775bb9bd-chunk-0027","chunkIndex":26,"heading":"1.4.3. GPIO Functions","headingPath":["1.4.3. GPIO Functions"],"preview":"","images":[],"readUrl":"https://www.embedr.app/api/datasheets/ds_5d5844c3162e775bb9bd/chunks/ds_5d5844c3162e775bb9bd-chunk-0027"},{"chunkId":"ds_5d5844c3162e775bb9bd-chunk-0028","chunkIndex":27,"heading":"1.4.3. GPIO Functions","headingPath":["1.4.3. GPIO Functions"],"preview":"Table 3. GPIO bank 0 function descriptions","images":[],"readUrl":"https://www.embedr.app/api/datasheets/ds_5d5844c3162e775bb9bd/chunks/ds_5d5844c3162e775bb9bd-chunk-0028"},{"chunkId":"ds_5d5844c3162e775bb9bd-chunk-0029","chunkIndex":28,"heading":"1.4.3. GPIO Functions","headingPath":["1.4.3. GPIO Functions"],"preview":"Chapter 2. System Description This chapter describes the RP2040 key system features including processor, memory, how blocks are connected, clocks, resets, power, and IO. Refer to Figure 2 for an overview diagram. 2.1. Bus Fabric The RP2040","images":[],"readUrl":"https://www.embedr.app/api/datasheets/ds_5d5844c3162e775bb9bd/chunks/ds_5d5844c3162e775bb9bd-chunk-0029"},{"chunkId":"ds_5d5844c3162e775bb9bd-chunk-0030","chunkIndex":29,"heading":"2.1. Bus Fabric","headingPath":["2.1. Bus Fabric"],"preview":"B F[\"SRAM0 64 kB\"] B G[\"SRAM1 64 kB\"] B H[\"SRAM2 64 kB\"] B I[\"SRAM3 64 kB\"] B J[\"SRAM4 4 kB\"] B K[\"SRAM5 4 kB\"] B L[\"APB Bridge\"] M[\"Control\"] B N[\"AHB Lite Splitter\"] O[\"Flash XIP\"] N P[\"PIO0\"] N Q[\"PIO1\"] N R[\"USB\"] S[\"APB Splitter\"] T[\"U","images":[],"readUrl":"https://www.embedr.app/api/datasheets/ds_5d5844c3162e775bb9bd/chunks/ds_5d5844c3162e775bb9bd-chunk-0030"},{"chunkId":"ds_5d5844c3162e775bb9bd-chunk-0031","chunkIndex":30,"heading":"2.1. Bus Fabric","headingPath":["2.1. Bus Fabric"],"preview":"The four bus masters can access any four different crossbar ports simultaneously, the bus fabric does not add wait states to any AHB Lite slave access. So at a system clock of 125MHz the maximum sustained bus bandwidth is 2.0GBps. The syste","images":[],"readUrl":"https://www.embedr.app/api/datasheets/ds_5d5844c3162e775bb9bd/chunks/ds_5d5844c3162e775bb9bd-chunk-0031"},{"chunkId":"ds_5d5844c3162e775bb9bd-chunk-0032","chunkIndex":31,"heading":"2.1.1. AHB-Lite Crossbar","headingPath":["2.1.1. AHB-Lite Crossbar"],"preview":"2.1.1. AHB Lite Crossbar At the centre of the RP2040 bus fabric is a 4:10 fully connected crossbar. Its 4 upstream ports are connected to the 4 system bus masters, and the 10 downstream ports connect to the highest bandwidth AHB Lite slaves","images":[],"readUrl":"https://www.embedr.app/api/datasheets/ds_5d5844c3162e775bb9bd/chunks/ds_5d5844c3162e775bb9bd-chunk-0032"},{"chunkId":"ds_5d5844c3162e775bb9bd-chunk-0033","chunkIndex":32,"heading":"2.1.1. AHB-Lite Crossbar","headingPath":["2.1.1. AHB-Lite Crossbar"],"preview":"M[\"Downstream Port 2\"] D ```","images":[],"readUrl":"https://www.embedr.app/api/datasheets/ds_5d5844c3162e775bb9bd/chunks/ds_5d5844c3162e775bb9bd-chunk-0033"},{"chunkId":"ds_5d5844c3162e775bb9bd-chunk-0034","chunkIndex":33,"heading":"2.1.1.1. Bus Priority","headingPath":["2.1.1.1. Bus Priority"],"preview":"2.1.1.1. Bus Priority The arbiters in the main AHB Lite crossbar implement a two level bus priority scheme. Priority levels are configured permaster, using the BUS\\ PRIORITY register in the BUSCTRL register block. When there are multiple si","images":[],"readUrl":"https://www.embedr.app/api/datasheets/ds_5d5844c3162e775bb9bd/chunks/ds_5d5844c3162e775bb9bd-chunk-0034"},{"chunkId":"ds_5d5844c3162e775bb9bd-chunk-0035","chunkIndex":34,"heading":"NOTE","headingPath":["NOTE"],"preview":"NOTE Priority arbitration only applies to multiple masters attempting to access the same slave on the same cycle. Accesses to different slaves, e.g. different SRAM banks, can proceed simultaneously. When accessing a slave with zero wait sta","images":[],"readUrl":"https://www.embedr.app/api/datasheets/ds_5d5844c3162e775bb9bd/chunks/ds_5d5844c3162e775bb9bd-chunk-0035"},{"chunkId":"ds_5d5844c3162e775bb9bd-chunk-0036","chunkIndex":35,"heading":"2.1.1.2. Bus Performance Counters","headingPath":["2.1.1.2. Bus Performance Counters"],"preview":"2.1.1.2. Bus Performance Counters The performance counters automatically count accesses to the main AHB Lite crossbar arbiters. This can assist in diagnosing performance issues, in high traffic use cases. There are four performance counters","images":[],"readUrl":"https://www.embedr.app/api/datasheets/ds_5d5844c3162e775bb9bd/chunks/ds_5d5844c3162e775bb9bd-chunk-0036"},{"chunkId":"ds_5d5844c3162e775bb9bd-chunk-0037","chunkIndex":36,"heading":"2.1.1.2. Bus Performance Counters","headingPath":["2.1.1.2. Bus Performance Counters"],"preview":"","images":[],"readUrl":"https://www.embedr.app/api/datasheets/ds_5d5844c3162e775bb9bd/chunks/ds_5d5844c3162e775bb9bd-chunk-0037"},{"chunkId":"ds_5d5844c3162e775bb9bd-chunk-0038","chunkIndex":37,"heading":"2.1.1.2. Bus Performance Counters","headingPath":["2.1.1.2. Bus Performance Counters"],"preview":"2.1.2. Atomic Register Access Each peripheral register block is allocated 4kB of address space, with registers accessed using one of 4 methods, selected by address decode. • Addr + 0x0000 : normal read write access • Addr + 0x1000 : atomic","images":[],"readUrl":"https://www.embedr.app/api/datasheets/ds_5d5844c3162e775bb9bd/chunks/ds_5d5844c3162e775bb9bd-chunk-0038"},{"chunkId":"ds_5d5844c3162e775bb9bd-chunk-0039","chunkIndex":38,"heading":"2.1.2. Atomic Register Access","headingPath":["2.1.2. Atomic Register Access"],"preview":"The four atomic access aliases occupy a total of 16kB. Most peripherals on RP2040 provide this functionality natively, and atomic writes have the same timing as normal read/write access. Some peripherals (I2C, UART, SPI and SSI) instead hav","images":[],"readUrl":"https://www.embedr.app/api/datasheets/ds_5d5844c3162e775bb9bd/chunks/ds_5d5844c3162e775bb9bd-chunk-0039"},{"chunkId":"ds_5d5844c3162e775bb9bd-chunk-0040","chunkIndex":39,"heading":"2.1.3. APB Bridge","headingPath":["2.1.3. APB Bridge"],"preview":"2.1.3. APB Bridge The APB bridge interfaces the high speed main AHB Lite interconnect to the lower bandwidth peripherals. Whilst the AHB Lite fabric offers zero wait state access everywhere, APB accesses have a cycle penalty: • APB bus acce","images":[],"readUrl":"https://www.embedr.app/api/datasheets/ds_5d5844c3162e775bb9bd/chunks/ds_5d5844c3162e775bb9bd-chunk-0040"},{"chunkId":"ds_5d5844c3162e775bb9bd-chunk-0041","chunkIndex":40,"heading":"2.1.4. Narrow IO Register Writes","headingPath":["2.1.4. Narrow IO Register Writes"],"preview":"2.1.4. Narrow IO Register Writes Memory mapped IO registers on RP2040 ignore the width of bus read/write accesses. They treat all writes as though they were 32 bits in size. This means software can not use byte or halfword writes to modify","images":[],"readUrl":"https://www.embedr.app/api/datasheets/ds_5d5844c3162e775bb9bd/chunks/ds_5d5844c3162e775bb9bd-chunk-0041"},{"chunkId":"ds_5d5844c3162e775bb9bd-chunk-0042","chunkIndex":41,"heading":"2.1.4. Narrow IO Register Writes","headingPath":["2.1.4. Narrow IO Register Writes"],"preview":"io rw 32 scratch32 = &watchdog hw scratch[0]; // Alias the scratch register as two halfwords at offsets +0x0 and +0x2 volatile uint16 t scratch16 = (volatile uint16 t ) scratch32; // Alias the scratch register as four bytes at offsets +0x0,","images":[],"readUrl":"https://www.embedr.app/api/datasheets/ds_5d5844c3162e775bb9bd/chunks/ds_5d5844c3162e775bb9bd-chunk-0042"},{"chunkId":"ds_5d5844c3162e775bb9bd-chunk-0043","chunkIndex":42,"heading":"2.1.4. Narrow IO Register Writes","headingPath":["2.1.4. Narrow IO Register Writes"],"preview":"// Read back the whole scratch register in one go printf(\"Should be 0xa5a5a5a5: 0x%08x\\n\", scratch32); // The IO register ignores the address LSBs [1:0] as well as the transfer // size, so it doesn't matter what byte offset we use printf(\"\\","images":[],"readUrl":"https://www.embedr.app/api/datasheets/ds_5d5844c3162e775bb9bd/chunks/ds_5d5844c3162e775bb9bd-chunk-0043"},{"chunkId":"ds_5d5844c3162e775bb9bd-chunk-0044","chunkIndex":43,"heading":"2.1.5. List of Registers","headingPath":["2.1.5. List of Registers"],"preview":"2.1.5. List of Registers The Bus Fabric registers start at a base address of 0x40030000 (defined as BUSCTRL\\ BASE in SDK). Table 4. List of BUSCTRL registers","images":[],"readUrl":"https://www.embedr.app/api/datasheets/ds_5d5844c3162e775bb9bd/chunks/ds_5d5844c3162e775bb9bd-chunk-0044"},{"chunkId":"ds_5d5844c3162e775bb9bd-chunk-0045","chunkIndex":44,"heading":"BUSCTRL: BUS\\_PRIORITY Register","headingPath":["BUSCTRL: BUS\\_PRIORITY Register"],"preview":"BUSCTRL: BUS\\ PRIORITY Register Offset: 0x00 Description Set the priority of each master for bus arbitration. Table 5. BUS\\ PRIORITY Register","images":[],"readUrl":"https://www.embedr.app/api/datasheets/ds_5d5844c3162e775bb9bd/chunks/ds_5d5844c3162e775bb9bd-chunk-0045"},{"chunkId":"ds_5d5844c3162e775bb9bd-chunk-0046","chunkIndex":45,"heading":"BUSCTRL: BUS\\_PRIORITY\\_ACK Register","headingPath":["BUSCTRL: BUS\\_PRIORITY\\_ACK Register"],"preview":"BUSCTRL: BUS\\ PRIORITY\\ ACK Register Offset: 0x04 Description Bus priority acknowledge Table 6. BUS PRIORITY ACK Register","images":[],"readUrl":"https://www.embedr.app/api/datasheets/ds_5d5844c3162e775bb9bd/chunks/ds_5d5844c3162e775bb9bd-chunk-0046"},{"chunkId":"ds_5d5844c3162e775bb9bd-chunk-0047","chunkIndex":46,"heading":"BUSCTRL: PERFCTR0 Register","headingPath":["BUSCTRL: PERFCTR0 Register"],"preview":"BUSCTRL: PERFCTR0 Register Offset: 0x08 Description Bus fabric performance counter 0 Table 7. PERFCTR0 Register","images":[],"readUrl":"https://www.embedr.app/api/datasheets/ds_5d5844c3162e775bb9bd/chunks/ds_5d5844c3162e775bb9bd-chunk-0047"},{"chunkId":"ds_5d5844c3162e775bb9bd-chunk-0048","chunkIndex":47,"heading":"BUSCTRL: PERFSEL0 Register","headingPath":["BUSCTRL: PERFSEL0 Register"],"preview":"BUSCTRL: PERFSEL0 Register Offset: 0x0c Description Bus fabric performance event select for PERFCTR0 Table 8. PERFSEL0 Register","images":[],"readUrl":"https://www.embedr.app/api/datasheets/ds_5d5844c3162e775bb9bd/chunks/ds_5d5844c3162e775bb9bd-chunk-0048"},{"chunkId":"ds_5d5844c3162e775bb9bd-chunk-0049","chunkIndex":48,"heading":"Description","headingPath":["Description"],"preview":"BUSCTRL: PERFCTR1 Register Offset: 0x10 Description Bus fabric performance counter 1 Table 9. PERFCTR1 Register","images":[],"readUrl":"https://www.embedr.app/api/datasheets/ds_5d5844c3162e775bb9bd/chunks/ds_5d5844c3162e775bb9bd-chunk-0049"},{"chunkId":"ds_5d5844c3162e775bb9bd-chunk-0050","chunkIndex":49,"heading":"BUSCTRL: PERFSEL1 Register","headingPath":["BUSCTRL: PERFSEL1 Register"],"preview":"BUSCTRL: PERFSEL1 Register Offset: 0x14 Description Bus fabric performance event select for PERFCTR1 Table 10. PERFSEL1 Register","images":[],"readUrl":"https://www.embedr.app/api/datasheets/ds_5d5844c3162e775bb9bd/chunks/ds_5d5844c3162e775bb9bd-chunk-0050"}]}